VHDL of 8 bit Adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder8bit is
port ( a,b : in std_logic_vector (7 downto 0);
s : out std_logic_vector (7 downto 0);
cout : out std_logic);
end adder8bit;

architecture a of adder8bit is
signal y : std_logic_vector (8 downto 0);
begin
process (y,a,b)
begin
y (7 downto 0) <= a+b;
if a(7) = '1' then
if b(7) = '1' then
y(8) <= '1' ;
else
y(8) <= '0';
end if;
end if;
s <= y(7 downto 0);
cout <= y(8);
end process aa;
end a;