VHDL of 4 bit Multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity Mux4bit is
port ( s : in std_logic_vector(3 downto 0);
x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
m : out std_logic_vector(3 downto 0));
end entity Mux4bit;

architecture df of Mux4bit is
begin
m <= ((not s) and x) or (s and y);
end df;