Latches, Flip-flops, and Registers

2007/10/11
Class.
Write VHDL code of the following...

A gated RS latch circuit.
--A gated RS latch described the hard way
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY part1 IS
PORT( Clk,R,S:IN STD_LOGIC;
Q :OUT STD_LOGIC);
END part1;

ARCHITECTURE Structural OF part1 IS
SIGNAL R_g,S_g,Qa,Qb:STD_LOGIC;
ATTRIBUTE keep:boolean;
ATTRIBUTE keep of R_g,S_g,Qa,Qb:SIGNAL IS true;
BEGIN
R_g <= R AND Clk;
S_g <= S AND Clk;
Qa <= NOT(R_g OR Qb);
Qb <= NOT(S_g OR Qa);

Q< = Qa;

END Structural;

A behavioral style of VHDL code that specifies a gated D latch.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY latch IS
PORT (D,Clk :IN STD_LOGIC;
Q :OUT STD_LOGIC);
END latch;

ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS(D,Clk)
BEGIN
IF Clk = '1'THEN
Q <= D;
END IF;
END PROCESS;
END Behavior;

Recompile the circuit and download it into the FPGA chip.
library ieee;
use ieee.std_logic_1164.all;

entity part1 is
port(clk :std_logic;
d :in std_logic_vector(7 downto 0);
qb,qc :out std_logic_vector(7 downto 0));
end part1;

architecture structure of part1 is

begin
u2:process(d,clk)
begin
if (clk'event and (clk = '1')) then
end if;
end process;
u3:process(d,clk)
begin
if(clk'event and (clk = '0'))then
qc<=d;
end if;
end process;
end structure;