VHDL of Full Adder 4

VHDL of Full Adder 4
room416
2007/10/26
利用以下程式碼在 QuartusII 中執行並燒錄
燒錄完成後三位元加法器的顯示數字只有以下
3(011),2(010),1(001),0(000),-1(111),-2(110),-3(101),-4(100)
做出兩個數字相加不會爆 例如：1(001)+1(001)=2(010)
做出兩個數字相加會爆 例如：2(010)+2(010)=4(100) 因為爆而亮最左邊
做出兩個數字相加會爆且進位 例如：-3(101)+-3(101)=-6(010) 因為爆而且進位而亮最左邊及進位燈
　
library ieee;
use ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

entity full_adder_4 is
port(
-- cin : in std_logic := '0';
a,b : in std_logic_vector( 2 downto 0);
clock, enable : std_logic;
co : out std_logic;
ov : out std_logic;
sum : out std_logic_vector( 2 downto 0) );
end full_adder_4;

architecture struc of full_adder_4 is
signal tco : std_logic_vector( 3 downto 0);
component lpm_dff
generic( lpm_width : integer := 3);

port( data : in std_logic_vector( lpm_width -1 downto 0);
clock : std_logic;
enable : std_logic;
q : out std_logic_vector( lpm_width -1 downto 0)
);
end component;

component full_adder is
port( cin : std_logic;
a,b : std_logic;
co,s : out std_logic);
end component;

signal tra,trb : std_logic_vector( 2 downto 0);
begin
ra: lpm_dff
generic map( lpm_width => 3)
port map( a, clock, enable , tra);
rb: lpm_dff
generic map( lpm_width => 3)
port map( b, clock, enable , trb);

g1: for i in 0 to 2 generate
p1: if( i = 0 ) generate
fax: full_adder port map( '0', tra(0), trb(0), tco(0), sum(0));
end generate p1;
p2: if( i /=0 ) generate
fax: full_adder port map( tco(i-1), tra(i), trb(i), tco(i), sum(i));
end generate p2;

end generate g1 ;
co <= tco(2);
ov <= tco(2) xor tco(1);
end struc;

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port( cin,a,b : std_logic;
co,s : out std_logic);
end full_adder;

architecture df of full_adder is
begin

co <= ( a and b) or( cin and ( a xor b));
s <= cin xor ( a xor b);
end df;